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TC9470FN 2002-02-27 1 toshiba cmos digital integrated circuit silicon monolithic TC9470FN - ? modulation da converter with built-in 8-times oversampling digital filter/dynamic digital bass boost/analog filter the TC9470FN is a second-order - ? modulation system 1 -bit da converter incorporating an 8-times oversampling digital filter, dynamic digital bass boost function for use with compressor operations and an analog filter developed for digital audio equipment. because the ic includes an analog filter, it can output a direct analog waveform, thus reducing the size and cost of the da converter. features built-in 8-times oversampling digital filter low-voltage operations (2.4 v) possible built-in digital de-emphasis filter built-in dynamic digital bass boost function in serial control mode, output amplitude can be set in 4096 steps of resolution using microcontroller commands in parallel control mode, soft mute can be set for the output signal in 64 steps in 23 ms built-in lr common digital zero detection output circuit sampling frequency: 44. 1 khz supports 384 fs/256 fs (automatic switching) da converter oversampling ratio (osr): 1 92 fs (at 384 fs) stereo/monaural output selection possible built-in third-order analog filter the digital filter and da converter characteristics are shown on the next page digital filter digital filter passband ripple transient bandwidth attenuation standard operation 8 fs 0.11db 20 k to 24.1 khz ? 26db or less da converter (v dd = 2.7 v) osr noise distortion s/n ratio standard operation 192 fs ? 82db (typ.) 90db (typ.) weight: 0.14 g (typ.)
TC9470FN 2002-02-27 2 pin connection block diagram 24 bck data dbb2 a tt (dbb1) shift (emp) 23 22 21 20 19 18 v dd 1 2 3 4 5 6 7 t1 s p/ v d a ro gnd a v r latch (sm) 17 8 gnd a v dx 16 9 lo xo 15 10 v d a xi 14 11 zd gndx 13 12 gndd mck lrck lrck 24 23 22 21 20 19 18 17 16 15 14 13 data interface circuit microcontroller interface circuit oscillator circuit dynamic bus boost circuit timing generator digital filter circuit, de-emphasis filter circuit, attenuator circuit - ? modulator circuit output circuit test circuit analog filte r 1 2 3 4 5 6 7 8 9 10 11 12 output circuit analog filte r + bck data dbb2 (dbb1) att v dx xo xi gndx mck (emp) shift (sm) latch lo v da zd gndd s p/ v da vr gnda ro gnda v dd t1
TC9470FN 2002-02-27 3 pin function pin no. symbol i/o function remarks 1 v dd D digital block power supply pin 2 t1 i test pin. always set to ?low? level. 3 s p/ i parallel/serial mode select pin 4 v da D analog power supply pin 5 ro o right channel analog signal output pin 6 gnda D analog gnd pin 7 vr D reference voltage pin 8 gnda D analog gnd pin 9 lo o left channel analog signal output pin 10 v da D analog power supply pin 11 zd o zero data detection output pin common to left and right channels 12 gndd D digital gnd pin 13 mck o system clock output pin 14 gndx D crystal oscillator gnd pin 15 xi i 16 xo o crystal oscillator connecting pins. generate the clock required by the system. 17 v dx D crystal oscillator power supply pin 18 latch (sm) i in serial mode, data latch signal input pin in parallel mode, soft mute control pin schmidt input 19 shift (emp) i in serial mode, shift clock input pin in parallel mode, de-emphasis filter control pin schmidt input 20 att (dbb1) i in serial mode, data input pin in parallel mode, dynamic bass boost control pin 1 schmidt input 21 dbb2 i in parallel mode, dynamic bass boost control pin 2 22 data i audio data input pin schmidt input 23 bck i bit clock input pin schmidt input 24 lrck i lr clock input pin schmidt input xi xo
TC9470FN 2002-02-27 4 description of block operations 1. crystal oscillator circuit and timing generator the clock required for internal operations is generated by connecting a crystal and condensers as shown in the diagram below. the ic will also operate when a system clock is input from an external source through the xi pin (pin 1 5). however, in this situation, due consideration must be given to the fact that waveform characteristics, such as jitter and rising/falling characteristics of the system clock, significantly affect the da converter?s noise distortion and the s/n ratio. the timing generator generates the clocks and process timing signals required for such functions as digital filtering and de-emphasis filtering. figure 1 crystal oscillator circuit configuration (when in the 384 fs mode) c l = 10 to 33 pf to internal circuit gndx 16.9344 mhz c l xi xo v dx c l x?tal mck use a crystal with a low ci value and favorable start-up characteristics.
TC9470FN 2002-02-27 5 2. data input circuit data and the lrck are loaded to the lsi internal shift registers on the bck signal rising edge. it is consequently necessary fo r the data and lrck signals to be synchronized and input on the bck signal falling edge as indicated in the timing example below. also, as data has been designed so that the 1 6 bits before the change point of lrck are regarded as valid data, the data must be input with right-justified mode when the bck is 48 fs or 64 f s, as shown in figure 2a. figure 2a example of input timing chart l-ch r-ch lrck bck msb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 lsb msb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 lsb data figure 2b example of input timing chart invalid data invalid data l-ch r-ch lrck bck m s b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 l s b m s b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 l s b data
TC9470FN 2002-02-27 6 3. digital filter the 8-times oversampling iir digital filter eliminates the noise returned from outside the bandwidth during standard operations. table 1 basic characteristics of digital filter set mode passband ripple transient bandwidth attenuation standard operations 0.11db 20 k to 24.1 khz ? 26db or less the characteristics of the digital filter frequencies are shown below. 4. de-emphasis filter on/off is controlled in the parallel mode ( s p/ = ?h?) with the shift (emp) pin (pin 1 9). this is set in the serial mode ( s p/ = ?l?) with a microcontroller or other equipment. (refer to 1 0.2 microcontroller setting mode for further details on serial mode settings.) table 2 de-emphasis filter settings (when in the parallel mode) shift (emp) pin h l de-emphasis filter on off figure 3 digital filter frequency characteristics frequency (khz) gain (db) frequency (khz) gain (db) 0 44.1 88.2 132.3 176.4 ? 100.0 ? 80.00 ? 60.00 ? 40.00 ? 20.00 0.000 ? 90.00 ? 70.00 ? 50.00 ? 30.00 ? 10.00 0 2.0 10.0 14.0 18.0 24.0 ? 1.00 ? 0.80 ? 0.60 ? 0.40 ? 0.20 ? 0.00 4.0 6.0 8.0 12.0 16.0 20.0 22.0 ? 0.90 ? 0.70 ? 0.50 ? 0.30 ? 0.10 0.65db
TC9470FN 2002-02-27 7 the digitalization of the de-emphasis filter eliminates the need for such external components as resistors, condensers and analog switches. in addition to this, the coefficients are aligned to reduce error in the de-emphasis filter characteristics. the filter structure and characteristics are shown below. 5. dynamic digital bass boost circuit on/off for the dynamic digital bass boost is controlled in the parallel mode ( s p/ = ?h?) with the dbb 1 pin (pin 20) and the dbb2 pin (pin 2 1 ). this is set in the serial mode ( s p/ = ?l?) with a microcontroller or other equipment. (refer to 1 0.2 microcontroller setting mode for further details on serial mode settings.) a block diagram for the dynamic bass boost circuit is shown in figure 6. the compressor?s compression ratio when in the control mode for the parallel mode is shown below. table 3 compressor compression ratio (when in the parallel mode) dbb max 18db dbb mid 12db the compressor?s compression characteristics are as follows: table 4 compressor compression characteristics (when in the parallel mode) dbb max ? 36db dbb mid ? 24db figure 6 dynamic digital bass boost circuit block + input output serial attenuator compressor block l.p.f coefficient length: 7 bits figure 4 iir digital de-emphasis filter figure 5 filter characteristics |g (j )| 1 /t 1 2 /t 1 t 1 = 50 s, t 2 = 15 s + + input data b 0 a 1 b 1 z ? 1 1 1 1 1 0 z a (1 ) z b (b (z) h : function transfer
TC9470FN 2002-02-27 8 the compressor i/o characteristics for the dynamic digital bass boost are shown in figure 7. the bass boost settings when in the parallel mode are shown below. table 5 bass boost mode settings mode 1 mode 2 mode 3 mode 4 dbb1 (pin 20) l l h h dbb2 (pin 21) l h l h mode 1 : dbb off mode 2: dbb mid mode 3: dbb max mode 4: dbb max + hb figure 7 dynamic digital bass boost compressor i/o characteristics input level (db) compressor gain output (db) ? 100 ? 80 ? 60 ? 40 ? 20 0 ? 100 ? 80 ? 60 ? 40 ? 20 0 efs = ?l? ? 10 ? 30 ? 50 ? 70 ? 90 ? 90 ? 70 ? 50 ? 30 ? 10 efs = ?h?
TC9470FN 2002-02-27 9 the bus boost characteristics are shown in figure 8. figure 8 dynamic bass boost frequency characteristics (v dd = 2.7 v) a) vin = ? 36db input, dbb off, 1 khz = 0db. frequency (khz) response (db) 0.01 0.1 1 10 100 ? 10 ? 5 5 10 20 30 0 15 25 b) vin = ? 20db input, dbb off, 1 khz = 0db. compressor characteristics mid: efs = ?l? ( ? 24db) max: efs = ?h? ( ? 36db) maga: efs = ?h? ( ? 36db) frequency (khz) response (db) 0.01 0.1 1 10 100 ? 10 ? 5 5 10 20 30 0 15 25 c) vin = 0db input, dbb off, 1 khz = 0db. compressor?s compression characteristics mid: efs = ?l? ( ? 24db) max: efs = ?h? ( ? 36db) maga: efs = ?h? ( ? 36db) frequency (khz) response (db) 0.01 0.1 1 10 100 ? 10 ? 5 5 10 20 30 0 15 25 off mid max + hb mega + hb
TC9470FN 2002-02-27 10 6. da conversion circuit the ic incorporates a second-order - ? modulation da converter for two channels (simultaneous output type). the internal structure of this is shown in figure 9. the - ? modulation clock has been designed to operate at 1 92 fs (when 384 fs). the noise shaping characteristics are shown in figure 1 0. 7. data output circuit the output circuit is equipped with a third-order analog low-pass filter. this enables direct analog signals to be acquired from the ic?s ro (pin 5) and lo (pin 9) output pins. + + + 2 q z ? 1 z ? 1 x (z) y (z) data ? ? output data (bit-stream 1-bit da conversion data) limiter second-order - ? converter: y (z) = x (z) + (1 ? z ? 1 ) 2 q (z) figure 9 - ? modulation da converter frequency (hz) noise power (db) 0 500 k 1 m 10db figure 10 noise shaping characteristics pdm signals ro (lo) vr figure 11 analog filter circuit
TC9470FN 2002-02-27 11 8. soft mute circuit the ic is equipped with a soft mute function, and this enables a soft mute to be set for the da converter output by switching the sm pin (pin 1 8) from the ?l? level to the ?h? level when in the parallel mode ( s p/ = ?h?). the soft mute?s on/off function and the da converter output are shown in figure 1 2. the soft mute on/off control function is disabled during level transition. 9. common left channel/right channel digital zero data detection output circuit the ic is equipped with a common left channel/right channel digital zero data detection output circuit, and the zd pin (pin 11 ) is switched from ?l? to ?h? when data for both the left channel and the right channel becomes zero data for approximately 350 ms or longer. this is fixed at ?l? when the data for the left channel and right channel is not zero data. 10. description of internal control signals the s p/ pin can be used to switch between the parallel mode ( s p/ pin = ?h? in dc setting mode) and the serial mode ( s p/ pin = ?l? with the microcontroller interface function). 10.1 parallel mode ( s p/ = ?h?: dc setting mode) pins 1 8, 1 9, 20 and 2 1 are used as the mode setting pins shown in the table below when in the parallel mode. table 6 pin names at the parallel mode pin no. pin name pin description 18 sm soft mute control pin 19 emp de-emphasis control pin 20 dbb1 digital bass boost mode control pin 1 21 dbb2 digital bass boost mode control pin 2 sm pin input da converter output level approximately 23 ms off on off approximately 23 ms 64 1 64 1 figure 12 changes in the soft mute da converter output level
TC9470FN 2002-02-27 12 10.2 serial mode ( s p/ = ?l?: microcontroller setting mode) it is possible to make the various settings with a microcontroller when in the serial mode. pins 1 8, 1 9 and 20 are used as the command input pins shown in the table below when in the serial mode. table 7 pin names at the serial mode pin no. pin name pin description 18 latch data latch signal input pin 19 shift shift clock signal input pin 20 att data input pin the latch signals and att signals are loaded to the lsi internal shift registers on the shift signal rising edge. it is consequently necessary for the data input from the att pin on the shift signal rising edge to be valid as indicated in the timing example in figure 1 3. it is also necessary for the latch pulse to rise at least 1 .5 s after the final clock rising edge input from the shift pin. operating the shift clock with latch low destabilizes the internal state, which may lead to malfunctions, so it must therefore be set to the low level after loading d7 to the register. the various control settings when in the serial mode are shown in the table below. ensure that all control bits are set when the power supply is turned on. table 8 serial mode control settings control signals serial input data mode 1 mode 2 mode 3 d12 0 1 1 d11 at11 0 1 d10 at10 emp dbb1 d09 at09 mono dbb2 d08 at08 chs dbb3 d07 at07 rls bmute d06 at06 efs tca d05 at05 doff tcr d04 at04 D D d03 at03 D D d02 at02 D D d01 at01 D D d00 at00 D D at 11 to at00: attenuation level setting emp: de-emphasis on/off switch mono, chs: stereo/monaural switch rls: lrck polarity switch efs: dynamic circuit compression characteristics switch doff: dynamic circuit on/off switch dbb 1 , dbb2: digtal bass boost mode setting dbb3: dbb mega max setting bmute: bass boost mute tca: attack time switch tcr: recovery time switch figure 13 example of data setting timing in the serial mode d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 latch shift att a = 1.5 s or higher, b = 1.5 s or higher
TC9470FN 2002-02-27 13 10.2.1 setting mode 1 serial setting mode 1 is enabled when d 1 2 = ?l?. ( 1 ) digital attenuator the digital attenuation command is enabled when d 1 2 = l. the attenuation data can be set in 4096 different ways (coefficient: 1 2 bit, maximum attenuation: ? 72.245db). the relationship with the command?s output is shown below. table 9 attenuation data/audio data output attenuation data at [11:00] audio output fffh ? 0.000db ffeh ? 0.002db ffbh ? 0.004db c80h ? 2.142db 640h ? 8.163db 002h ? 66.224db 001h ? 72.245db 000h ? 00 1 (hex) to ffe (hex): the attenuation value is obtained with the following equation. att = 20 ? og (input data/4095) db example: when the attenuation data is ea0h att = 20 ? og (4000/4095) db = ? 0.204db if an input level is set to ? 48db or less when it is set as the amount ( ? 72.245db) of the maximum attenuation, the target effective attenuation data of digital attenuator of TC9470FN will be lost. the output data is set to ?0? when an input level is set to ? 48db or less. an effective input level is decided by the following formula. effective input data = ? [ 1 20db + attenuation level (db)] 10.2.2 setting mode 2 serial setting mode 2 is enabled when d 1 2 = ?h? and d 11 = ?l?. ( 1 ) digital de-emphasis filter controlled with emp. table 10 digital de-emphasis filter setting emp l h de-emphasis filter off on
TC9470FN 2002-02-27 14 (2) stereo/monaural output channel settings set with mono and chs. table 11 stereo, monaural and channel select settings mono l h h chs (note) l h l, r-ch output stereo output l-ch monaural output r-ch monaural output note: ?h? or ?l? (3) lrch (channel clock) polarity switch settings set with rls. table 12 lrck polarity switch settings rls l h data input r-ch data when lrck = ?l? l-ch data when lrck = ?l? (4) compressor?s compression characteristics switch settings set with efs. table 13 compressor compression characteristics (compression ratio) settings efs l h compressor?s compression characteristics ? 24db ? 36db compressor compression ratio 12db 18db compressor?s compression characteristics and compression ratio are shown in figure 7. (5) dynamic circuit on/off switch settings set with doff. table 14 dynamic circuit on/off switch settings doff l h dynamic circuit on off the dynamic circuit?s on/off switch settings become invalid when dbb3 is set to ?h? in the following mode 2 settings. the amount of boost when the dynamic circuit is off is shown in table 1 5. table 15 amount of boost when the dynamic circuit is off amount of boost mid 10.6db max 15.2db
TC9470FN 2002-02-27 15 10.2.3 setting mode 3 serial setting mode 3 is enabled when d7 = ?h? and d6 = ?h?. ( 1 ) digital bass boost mode settings set with dbb 1 , dbb2 and dbb3. table 16 bass boost mode settings mode 1 mode 2 mode 3 mode 4 dbb1 l l h h dbb2 l h l h dbb3 l or h l or h l or h l or h the dbb3 settings are as follows. dbb3 = ?l? dbb3 = ?h? mode 1 : dbb off mode 2: dbb mid mode 3: dbb max mode 4: dbb max + hb mode 1 ?: dbb off mode 2?: dbb max mode 3?: dbb mega max mode 4?: dbb mega max + hb (2) bass boost mute setting set with bmute. the bass boost mute to be set for bass boost signal by switching the bmute from the ?l? level to the ?h? level. table 17 bass boost mute setting bmute l h bass boost mute off on time constant of bass boost mute: approximately 3.8 ms (3) attack time/recovery time switch settings set with tca for attack time and tcr for recovery time. table 18 attack time settings tca l h attack time 6.3 ms 24.3 ms table 19 recovery time settings tca l h recovery time 12.3 s 24.6 s
TC9470FN 2002-02-27 16 maximum ratings (ta = 25c) characteristics symbol rating unit v dd ? 0.3 to 6.0 v da ? 0.3 to 6.0 power supply voltage v dx ? 0.3 to 6.0 v input voltage v in ? 0.3 to v dd + 0.3 v power dissipation p d 200 mw operating temperature t opr ? 15 to 50 c storage temperature t stg ? 55 to 150 c electrical characteristics (unless otherwise specified, ta = 25c, v dd = v dx = v da = 2.7 v) dc characteristics characteristics symbol test circuit test condition min typ. max unit v dd 2.4 2.7 3.5 v dx 2.4 2.7 3.5 operating power supply voltage v da D ta = ? 15 to 50c 2.4 2.7 3.5 v current consumption i dd D xi = 16.9344 mhz v dd = v dx = 2.4 v D 4.0 5.5 ma ?h? level v ih v dd 0.7 D v dd input voltage ?l? level v il D 0 D v dd 0.3 v ?h? level i ih input current ?l? level i il D ? 10 D 10 a ac characteristics (oversampling ratio = 192 fs) characteristics symbol test circuit test condition min typ. max unit noise distortion thd + n 1 1 khz sine wave, full-scale input v dd = v dx = v da = 2.7 v D ? 82 ? 77 db s/n ratio s/n 1 v dd = v dx = v da = 2.7 v 85 90 D db dynamic range dr 1 1 khz sine wave, ? 60db input conversion 85 90 D db crosstalk ct 1 1 khz sine wave, full-scale input D ? 90 ? 80 db analog output level aout 1 1 khz sine wave, full-scale input v dd = v dx = v da = 2.7 v D 685 D mv rms operating frequency f opr D v dd = v dx = v da 2.4 v 11 16.9344 D mhz f lr lrck duty cycle = 50% D 44.1 D khz input frequency f bck D bck duty cycle = 50% 1.4 2.1168 2.9 mhz rise time t r D D D 15 ns fall time t f D lrck, bck pins (10% to 90%) D D 15 ns delay time t d D bck edge lrck, data D D 50 ns
TC9470FN 2002-02-27 17 test circuit 1 : with the use of a sample application circuit sg: anritsu: mg-22a or equivalent lpf: shibasoku: built-in 725c distortion factor gauge filter distortion: shibasoku: 725c or equivalent parameter measured distortion factor gauge filter setting a weight thd + n, ct off s/n, dr on a weight: iec-a or equivalent ac characteristics stipulated point (input signal stipulation: lrck, bck, data) application circuit the following diagram is for reference purposes only and does not guarantee operations. s g data bck lrck lout rout application circuit example 20 khz ideal lpf distortion factor gauge mck bck data lrck 50% 50% 50% 10% 10% 90% 90% t d t d t f t f mck gndd gndx xi xo v dx latch ( sm ) shift (emp) a tt (dbb1) data bcx lrck (dbb2) zd v da lo gnd a v r gnda ro v da s p/ t1 v dd xi emph aout bck chck 30 pf 30 pf 16.9344 m 2.7 v 2.7 v 2.7 v zd 220 ? 220 ? 2.7 v 2.7 v l-ch analog out r-ch analog out tc9236af single-chip processor for cd players 10 k ? 10 k ? 2200 pf 2200 pf 22 f 100 f 100 f 100 f 100 f TC9470FN
TC9470FN 2002-02-27 18 package dimensions weight: 0.14 g (typ.)
TC9470FN 2002-02-27 19 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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